A distinguishable faults test generation method for digital circuits is presented . the features of basic gate circuits and neural networks are used to establish the test model , and to generate the test patterns for given faults . the fault model and constrained circuit are studied . some strategies , e . g , the reduction of the size of neural network , are proposed in order to accelerate test generation process . the experimental results demonstrate that the algorithm proposed in the paper is effective 研究一種基于人工神經(jīng)網(wǎng)絡(luò)的能區(qū)分故障的數(shù)字電路測試生成方法,該方法利用電路基本邏輯門的特性和神經(jīng)網(wǎng)絡(luò)模型的特點,首先建立測試生成的神經(jīng)網(wǎng)絡(luò)模型,然后通過求解網(wǎng)絡(luò)能量函數(shù)的最小值點獲得給定類型故障的測試矢量,其研究結(jié)果在可區(qū)分故障的測試生成方面提供了一種可能的新途徑